1. FIELD OF THE INVENTION
The present invention relates to an integrated circuit package.
2. BACKGROUND INFORMATION
Integrated circuits are typically assembled into packages that are soldered to printed circuit boards. There are many types of integrated circuit packages including ball grid array (BGA) packages.
FIG. 1 shows a BGA package of the prior art. The package includes a substrate 1 that supports an integrated circuit 2. The integrated circuit 2 is typically wire bonded to bond fingers (not shown) on the top surface of the substrate. The bottom surface of the substrate 1 has a plurality of contact pads 3 that are electrically connected to the integrated circuit 2 by the bond fingers and vias that extend through the substrate 1. Solder balls 4 are attached to the contact pads 3 and then subsequently reflowed to mount the package to a printed circuit board (not shown).
As shown in FIG. 2, layers of solder mask 5 are applied to the bottom surface of the substrate 1 and then etched in certain locations to expose the contact pads 3. The solder mask 5 prevents shorting between the solder balls 4 when the solder is reflowed onto a printed circuit board. It has been found that the etching processes creates an annular lip 6 in the solder mask 5. The lip 6 creates a stress riser in the solder joint which may induce a crack 7 in the solder. The crack 7 may lead to a failure in the solder joint and render the integrated circuit package inoperable. It would be desirable to provide a BGA integrated circuit package and a process for forming the package that reduces the stress risers in the solder joints.